Design and analysis of CMOS Inverter and D Latch MCML Inverter

In this paper, a new D-latch topology has been implemented in MOS Current Mode Logic (MCML) that works on lower supply voltage than the D-latch topology already implemented in MCML. The already implemented D-latch topology is called Traditional DLatch Topology and the new D-latch topology that works on lower voltage is called low-voltage D-Latch Topology. Power consumed by MCML circuit is directly related to the supply voltage given to the circuit. For a particular amount of current drawn from the power supply, if supply voltage increases then power consumption of the circuit also increases and vice versa. Thus, the low-voltage D-latch topology consumes lesser power than the traditional D-latch topology.